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chipsalliance
verible chipsalliance
214
1.4k
other
48
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
yacc lexer linter parser sv-lrm verible analysis formatter lsp-server syntax-tree productivity style-linter hacktoberfest systemverilog systemverilog-parser systemverilog-developer language-server-protocol
Created 2019-11-07
3,842 commits to master branch, last one 6 days ago
Nic30
hdlConvertor Nic30
66
281
mit
23
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
fpga vhdl antrl4 parser python verilog vhdl-parser systemverilog verilog-parser systemverilog-parser
Created 2016-06-28
1,768 commits to master branch, last one 10 months ago