PrincetonUniversity / AutoSVA

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

Date Created 2021-04-01 (3 years ago)

Commits 18 (last one 8 months ago)

Stargazers 75 (0 this week)

Watchers 6 (0 this week)

Forks 24

License other

Ranking

RepositoryStats indexes 596,206 repositories, of these PrincetonUniversity/AutoSVA is ranked #357,841 (40th percentile) for total stargazers, and #300,747 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #67,612/119,532.

PrincetonUniversity/AutoSVA is also tagged with popular topics, for these it's ranked: design (#486/662), verilog (#195/289)

Other Information

There have been 1 release, the latest one was published on 2023-11-27 (about a year ago) with the name Reproduce Evaluation of DAC'21 paper.

Homepage URL: https://blog.yosyshq.com/p/community-spotlight-autosva/

All Topics

rtl sva design verilog verification systemverilog methodology-development

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Recent Commit History

10 commits on the default branch (master) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-12-11 @ 05:22pm, id: 353737142 / R_kgDOFRWZtg