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PrincetonUniversity
AutoSVA PrincetonUniversity
22
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other
6
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate l...
rtl sva design verilog verification systemverilog methodology-development
Created 2021-04-01
18 commits to master branch, last one 7 months ago