Trending repositories for topic systemverilog

Veryl: A Modern Hardware Description Language

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Control and status register code generator toolchain

Haskell to VHDL/Verilog/SystemVerilog compiler

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

Code generation tool for control and status registers

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Control and status register code generator toolchain

Veryl: A Modern Hardware Description Language

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Code generation tool for control and status registers

Haskell to VHDL/Verilog/SystemVerilog compiler

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Veryl: A Modern Hardware Description Language

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Haskell to VHDL/Verilog/SystemVerilog compiler

SystemVerilog compiler and language services

RISC-V Linux SoC, marchID: 0x2b

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Control and status register code generator toolchain

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

Functional verification project for the CORE-V family of RISC-V cores.

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

No description

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Code generation tool for control and status registers

AMBA AXI VIP

Send video/audio over HDMI on an FPGA

No description

Veryl: A Modern Hardware Description Language

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

Control and status register code generator toolchain

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

SystemVerilog compiler and language services

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Functional verification project for the CORE-V family of RISC-V cores.

RISC-V Linux SoC, marchID: 0x2b

Haskell to VHDL/Verilog/SystemVerilog compiler

Code generation tool for control and status registers

AMBA AXI VIP

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Send video/audio over HDMI on an FPGA

RISC-V Linux SoC, marchID: 0x2b

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Veryl: A Modern Hardware Description Language

SystemVerilog compiler and language services

Functional verification project for the CORE-V family of RISC-V cores.

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

SystemVerilog to Verilog conversion

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Методические материалы по разработке процессора архитектуры RISC-V

Control and status register code generator toolchain

AMBA AXI VIP

Haskell to VHDL/Verilog/SystemVerilog compiler

HDL support for VS Code

Code generation tool for control and status registers

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Send video/audio over HDMI on an FPGA

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

RISC-V Zve32x Vector Coprocessor

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

No description

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

Control and status register code generator toolchain

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate l...

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://na...

A Single Cycle Risc-V 32 bit CPU

Методические материалы по разработке процессора архитектуры RISC-V

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Veryl: A Modern Hardware Description Language

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

Functional verification project for the CORE-V family of RISC-V cores.

RISC-V Linux SoC, marchID: 0x2b

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://na...

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

RISC-V Linux SoC, marchID: 0x2b

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Veryl: A Modern Hardware Description Language

SystemVerilog compiler and language services

SystemVerilog to Verilog conversion

Send video/audio over HDMI on an FPGA

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Functional verification project for the CORE-V family of RISC-V cores.

Haskell to VHDL/Verilog/SystemVerilog compiler

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Методические материалы по разработке процессора архитектуры RISC-V

A simple superscalar out-of-order RISC-V microprocessor

Code generation tool for control and status registers

AMBA AXI VIP

SystemVerilog language server

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

An abstraction library for interfacing EDA tools

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Making cocotb testbenches that bit easier

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

No description

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

Package manager and build tool for VHDL/SystemVerilog

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Методические материалы по разработке процессора архитектуры RISC-V

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

A simple superscalar out-of-order RISC-V microprocessor

A Single Cycle Risc-V 32 bit CPU

10G Low Latency Ethernet

Control and status register code generator toolchain

RISC-V Linux SoC, marchID: 0x2b

Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Advanced Architecture Labs with CVA6