Trending repositories for topic systemverilog

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

RISC-V Linux SoC, marchID: 0x2b

SystemVerilog to Verilog conversion

Send video/audio over HDMI on an FPGA

SystemVerilog compiler and language services

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

RISC-V Linux SoC, marchID: 0x2b

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog to Verilog conversion

SystemVerilog compiler and language services

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Send video/audio over HDMI on an FPGA

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

RISC-V Linux SoC, marchID: 0x2b

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An abstraction library for interfacing EDA tools

SystemVerilog compiler and language services

SystemVerilog to Verilog conversion

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

Code generation tool for control and status registers

Functional verification project for the CORE-V family of RISC-V cores.

Send video/audio over HDMI on an FPGA

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Package manager and build tool for HDLs

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

Методические материалы по разработке процессора архитектуры RISC-V

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Haskell to VHDL/Verilog/SystemVerilog compiler

Package manager and build tool for HDLs

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

RISC-V Linux SoC, marchID: 0x2b

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Методические материалы по разработке процессора архитектуры RISC-V

SystemVerilog compiler and language services

An abstraction library for interfacing EDA tools

Code generation tool for control and status registers

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

SystemVerilog to Verilog conversion

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Functional verification project for the CORE-V family of RISC-V cores.

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Send video/audio over HDMI on an FPGA

Haskell to VHDL/Verilog/SystemVerilog compiler

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Veryl: A Modern Hardware Description Language

SystemVerilog to Verilog conversion

RISC-V Linux SoC, marchID: 0x2b

SystemVerilog compiler and language services

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

An abstraction library for interfacing EDA tools

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Control and status register code generator toolchain

Send video/audio over HDMI on an FPGA

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Haskell to VHDL/Verilog/SystemVerilog compiler

AMBA AXI VIP

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Test suite designed to check compliance with the SystemVerilog standard.

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

A Single Cycle Risc-V 32 bit CPU

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

A Single Cycle Risc-V 32 bit CPU

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Control and status register code generator toolchain

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

IEEE 754 single and double precision floating point library in systemverilog and vhdl

10G Low Latency Ethernet

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

复旦大学 数字逻辑与部件设计实验 2020秋

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Advanced Architecture Labs with CVA6

Many peripherals in Verilog ready to use

Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Veryl: A Modern Hardware Description Language

Методические материалы по разработке процессора архитектуры RISC-V

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

RISC-V Linux SoC, marchID: 0x2b

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Veryl: A Modern Hardware Description Language

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Send video/audio over HDMI on an FPGA

SystemVerilog to Verilog conversion

Haskell to VHDL/Verilog/SystemVerilog compiler

SystemVerilog compiler and language services

Методические материалы по разработке процессора архитектуры RISC-V

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Functional verification project for the CORE-V family of RISC-V cores.

AMBA AXI VIP

SystemVerilog language server

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

An abstraction library for interfacing EDA tools

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Code generation tool for control and status registers

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

A hardware component library developed with ROHD.

Методические материалы по разработке процессора архитектуры RISC-V

No description

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Package manager and build tool for HDLs

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

A Single Cycle Risc-V 32 bit CPU

Veryl: A Modern Hardware Description Language

Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components

Advanced Architecture Labs with CVA6

Control and status register code generator toolchain

RISC-V Linux SoC, marchID: 0x2b

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

10G Low Latency Ethernet

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

An FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器，可实现视频压缩。