WangXuan95 / FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

WangXuan95
WangXuan95
Date Created 2019-07-15 (5 years ago)
Commits 23 (last one about a year ago)
Stargazers 151 (0 this week)
Watchers 5 (0 this week)
Forks 25
License gpl-3.0
Ranking

RepositoryStats indexes 595,856 repositories, of these WangXuan95/FPGA-FixedPoint is ranked #221,305 (63rd percentile) for total stargazers, and #335,688 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #154/563.

WangXuan95/FPGA-FixedPoint is also tagged with popular topics, for these it's ranked: pipeline (#173/442),  verilog (#121/289)

Other Information

Homepage URL: https://gitee.com/wangxuan95/FPGA-FixedPoint

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

8 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

updated: 2024-12-21 @ 11:21am, id: 196991907 / R_kgDOC73bow