WangXuan95 / FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Date Created 2019-07-15 (5 years ago)

Commits 23 (last one about a year ago)

Stargazers 170 (0 this week)

Watchers 4 (0 this week)

Forks 31

License gpl-3.0

Ranking

RepositoryStats indexes 640,537 repositories, of these WangXuan95/FPGA-FixedPoint is ranked #213,142 (67th percentile) for total stargazers, and #368,429 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #147/632.

WangXuan95/FPGA-FixedPoint is also tagged with popular topics, for these it's ranked: pipeline (#165/464), verilog (#115/313), systemverilog (#40/102)

Other Information

Homepage URL: https://gitee.com/wangxuan95/FPGA-FixedPoint

All Topics

rtl verilog pipeline arithmetic fixedpoint systemverilog

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Github watchers over time, collection started in '23

Recent Commit History

8 commits on the default branch (master) since jan '22

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

updated: 2025-04-09 @ 09:17pm, id: 196991907 / R_kgDOC73bow