davemuscle / sigma_delta_converters

Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components

Date Created 2022-01-24 (2 years ago)

Commits 112 (last one 2 years ago)

Stargazers 40 (0 this week)

Watchers 5 (0 this week)

Forks 7

License unknown

Ranking

RepositoryStats indexes 523,840 repositories, of these davemuscle/sigma_delta_converters is ranked #468,897 (10th percentile) for total stargazers, and #314,188 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #130/152.

davemuscle/sigma_delta_converters is also tagged with popular topics, for these it's ranked: fpga (#399/425)

Other Information

davemuscle/sigma_delta_converters has Github issues enabled, there is 1 open issue and 1 closed issue.

There have been 1 release, the latest one was published on 2022-02-24 (2 years ago) with the name v1.0.0.

Homepage URL: http://davemuscle.com

All Topics

adc dac pwm fpga max10 quarkus decimation comb-filter sigma-delta systemverilog sigma-delta-modulation

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112 commits on the default branch (master) since jan '22

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The primary language is SystemVerilog but there's also others...

updated: 2024-05-27 @ 06:42am, id: 451284823 / R_kgDOGuYPVw