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davemuscle
sigma_delta_converters davemuscle
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7
Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
adc dac pwm fpga max10 quarkus decimation comb-filter sigma-delta systemverilog sigma-delta-modulation
Created 2022-01-24
112 commits to master branch, last one 2 years ago