WangXuan95 / FPGA-CAN

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Date Created 2021-05-08 (3 years ago)

Commits 10 (last one 9 months ago)

Stargazers 186 (0 this week)

Watchers 7 (0 this week)

Forks 56

License gpl-3.0

Ranking

RepositoryStats indexes 534,880 repositories, of these WangXuan95/FPGA-CAN is ranked #177,322 (67th percentile) for total stargazers, and #259,002 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #108/459.

WangXuan95/FPGA-CAN is also tagged with popular topics, for these it's ranked: fpga (#145/435), verilog (#94/257)

Other Information

WangXuan95/FPGA-CAN has Github issues enabled, there is 1 open issue and 3 closed issues.

Homepage URL: https://gitee.com/wangxuan95/FPGA-CAN

All Topics

can rtl fpga can-bus verilog controller systemverilog control-area-network

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

8 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-06-18 @ 04:05am, id: 365439563 / R_kgDOFcgqSw