openhwgroup / cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

openhwgroup
openhwgroup
Date Created 2022-02-08 (3 years ago)
Commits 580 (last one 5 days ago)
Stargazers 80 (0 this week)
Watchers 17 (0 this week)
Forks 19
License apache-2.0
Ranking

RepositoryStats indexes 630,459 repositories, of these openhwgroup/cva5 is ranked #356,225 (43rd percentile) for total stargazers, and #126,789 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #101/196.

Other Information

openhwgroup/cva5 has Github issues enabled, there are 4 open issues and 11 closed issues.

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

219 commits on the default branch (master) since jan '22

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Issue History

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Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogC++C++PythonPythonMakefileMakefile

updated: 2025-03-19 @ 05:23pm, id: 457069453 / R_kgDOGz5TjQ