Trending repositories for language SystemVerilog
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
A Linux-capable RISC-V multicore for and by the world
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Методические материалы по разработке процессора архитектуры RISC-V
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches,...
Project F brings FPGAs to life with exciting open-source designs you can build on.
A Linux-capable RISC-V multicore for and by the world
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A Linux-capable RISC-V multicore for and by the world
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches,...
Project F brings FPGAs to life with exciting open-source designs you can build on.
BaseJump STL: A Standard Template Library for SystemVerilog
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
Методические материалы по разработке процессора архитектуры RISC-V
Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog