Trending repositories for language SystemVerilog

A minimal GPU design in Verilog to learn how GPUs work from the ground up

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OpenSource GPU, in Verilog, loosely based on RISC-V ISA

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Send video/audio over HDMI on an FPGA

No description

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Send video/audio over HDMI on an FPGA

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

No description

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A simple superscalar out-of-order RISC-V microprocessor

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches,...

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Send video/audio over HDMI on an FPGA

Common SystemVerilog components

Project F brings FPGAs to life with exciting open-source designs you can build on.

RSD: RISC-V Out-of-Order Superscalar Processor

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

Методические материалы по разработке процессора архитектуры RISC-V

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

OpenTitan: Open source silicon root of trust

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

An uvm verification env for ahb2apb bridge

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AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

An uvm verification env for ahb2apb bridge

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

A simple superscalar out-of-order RISC-V microprocessor

A minimal GPU design in Verilog to learn how GPUs work from the ground up

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches,...

Методические материалы по разработке процессора архитектуры RISC-V

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

VIP for AXI Protocol

Common SystemVerilog components

Atari STE MiSTery core for the Tang Nano FPGAs

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Project F brings FPGAs to life with exciting open-source designs you can build on.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

A minimal GPU design in Verilog to learn how GPUs work from the ground up

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

OpenTitan: Open source silicon root of trust

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

RSD: RISC-V Out-of-Order Superscalar Processor

No description

Verilog evaluation benchmark for large language model

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Common SystemVerilog components

Atari STE MiSTery core for the Tang Nano FPGAs

SystemVerilog language-oriented exercises

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches,...

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

BlackParrot on Zynq

SystemVerilog language-oriented exercises

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

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SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

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MOS 6520 PIA / MOS 6522 VIA / MOS 6526/8520/8521 CIA replacement

Atari STE MiSTery core for the Tang Nano FPGAs

32-bit 5-Stage Pipelined RISC V RV32I Core

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HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

This is a detailed SystemVerilog course

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

AIA IP compliant with the RISC-V AIA spec

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.

No description

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

No description

Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )

Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

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Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

NTUEE Digital Circuit Lab 24Fall

FPGA cartridge for MSX

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

OpenTitan: Open source silicon root of trust

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Common SystemVerilog components

RSD: RISC-V Out-of-Order Superscalar Processor

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A Linux-capable RISC-V multicore for and by the world

Send video/audio over HDMI on an FPGA

Project F brings FPGAs to life with exciting open-source designs you can build on.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches,...

A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.

A Verilog synthesis flow for Minecraft redstone circuits

Verilog evaluation benchmark for large language model

BaseJump STL: A Standard Template Library for SystemVerilog

A Fast, Low-Overhead On-chip Network

No description

A minimal GPU design in Verilog to learn how GPUs work from the ground up

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

No description

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

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SystemVerilog language-oriented exercises

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

Методические материалы курса "Практикум по ПЛИС"

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

No description

A Fast, Low-Overhead On-chip Network

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tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )