Trending repositories for language SystemVerilog
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
BaseJump STL: A Standard Template Library for SystemVerilog
A Linux-capable RISC-V multicore for and by the world
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches,...
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A Linux-capable RISC-V multicore for and by the world
Project F brings FPGAs to life with exciting open-source designs you can build on.
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches,...
BaseJump STL: A Standard Template Library for SystemVerilog
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
Методические материалы по разработке процессора архитектуры RISC-V
Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )