karimmahmoud22 / SystemVerilog-For-Verification

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karimmahmoud22
karimmahmoud22
Date Created 2024-02-05 (about a year ago)
Commits 44 (last one 11 months ago)
Stargazers 27 (0 this week)
Watchers 2 (0 this week)
Forks 3
License mit
Ranking

RepositoryStats indexes 631,885 repositories, of these karimmahmoud22/SystemVerilog-For-Verification is ranked #614,328 (3rd percentile) for total stargazers, and #481,103 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #191/195.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

44 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

No issues have been posted

Languages

The only known language in this repository is SystemVerilog

SystemVerilogSystemVerilog

updated: 2025-03-18 @ 04:28am, id: 753227913 / R_kgDOLOVYiQ