rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor

rsd-devel
rsd-devel
Date Created 2019-12-11 (5 years ago)
Commits 406 (last one 8 months ago)
Stargazers 1,055 (0 this week)
Watchers 33 (0 this week)
Forks 103
License apache-2.0
Ranking

RepositoryStats indexes 631,351 repositories, of these rsd-devel/rsd is ranked #50,569 (92nd percentile) for total stargazers, and #65,255 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #7/195.

Other Information

rsd-devel/rsd has 5 open pull requests on Github, 45 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 15 open issues and 31 closed issues.

There have been 2 releases, the latest one was published on 2023-03-28 (about a year ago) with the name v1.1.0.

Star History

Github stargazers over time

1.2k1.2k1k1k80080060060040040020020000202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

343433.533.5333332.532.5323231.531.5313130.530.5303020232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

136 commits on the default branch (master) since jan '22

140140120120100100808060604040202000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

1601601401401201201001008080606040402020002019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
50504545404035353030252520201515101055002021202120222022202320232024202420252025

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogTclTclCCAssemblyAssemblyMakefileMakefilePythonPythonC++C++VerilogVerilogBatchfileBatchfileShellShell

updated: 2025-03-21 @ 04:05am, id: 227267635 / R_kgDODYvUMw