openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Date Created 2021-01-15 (3 years ago)

Commits 10,592 (last one 11 hours ago)

Stargazers 291 (0 this week)

Watchers 33 (0 this week)

Forks 200

License other

Ranking

RepositoryStats indexes 600,333 repositories, of these openhwgroup/cvw is ranked #139,157 (77th percentile) for total stargazers, and #66,314 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #31/183.

Other Information

openhwgroup/cvw has 4 open pull requests on Github, 870 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 23 open issues and 236 closed issues.

There have been 1 release, the latest one was published on 2023-04-27 (about a year ago) with the name Arty A7 board support, ImperasDV Linux boot.

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

8,253 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2025-01-05 @ 04:34am, id: 329806615 / R_kgDOE6hzFw