mbits-mirafra / SystemVerilogCourse

This is a detailed SystemVerilog course

mbits-mirafra
mbits-mirafra
Date Created 2022-06-30 (2 years ago)
Commits 362 (last one 20 days ago)
Stargazers 91 (0 this week)
Watchers 3 (0 this week)
Forks 40
License unknown
Ranking

RepositoryStats indexes 630,443 repositories, of these mbits-mirafra/SystemVerilogCourse is ranked #326,232 (48th percentile) for total stargazers, and #416,864 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #88/195.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

3333332.52.5222222Aug '23Aug '23Sep '23Sep '23Oct '23Oct '23Nov '23Nov '23Dec '23Dec '2320242024Feb '24Feb '24Mar '24Mar '24Apr '24Apr '24May '24May '24Jun '24Jun '24Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Recent Commit History

362 commits on the default branch (production) since jan '22

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Yearly Commits

Commits to the default branch (production) per year

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Issue History

No issues have been posted

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogMakefileMakefileBatchfileBatchfile

updated: 2025-03-18 @ 07:44am, id: 509037539 / R_kgDOHldL4w