aolofsson / oh

Verilog library for ASIC and FPGA designers

aolofsson
aolofsson
Date Created 2015-04-22 (9 years ago)
Commits 1,594 (last one 8 months ago)
Stargazers 1,223 (5 this week)
Watchers 100 (0 this week)
Forks 289
License mit
Ranking

RepositoryStats indexes 600,333 repositories, of these aolofsson/oh is ranked #42,997 (93rd percentile) for total stargazers, and #18,073 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #17/571.

Other Information

aolofsson/oh has 11 open pull requests on Github, 50 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 20 open issues and 16 closed issues.

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Recent Commit History

49 commits on the default branch (main) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2025-01-04 @ 02:49pm, id: 34361064 / R_kgDOAgxO6A