Arlet / verilog-6502

A Verilog HDL model of the MOS 6502 CPU

Arlet
Arlet
Date Created 2011-05-02 (13 years ago)
Commits 19 (last one about a year ago)
Stargazers 334 (1 this week)
Watchers 29 (0 this week)
Forks 93
License unknown
Ranking

RepositoryStats indexes 595,856 repositories, of these Arlet/verilog-6502 is ranked #124,146 (79th percentile) for total stargazers, and #75,927 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #68/563.

Other Information

Arlet/verilog-6502 has Github issues enabled, there are 4 open issues and 2 closed issues.

Homepage URL: http://c-scape.nl/arlet/fpga/6502/

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Recent Commit History

2 commits on the default branch (master) since jan '22

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Languages

The only known language in this repository is Verilog

updated: 2024-12-21 @ 02:23pm, id: 1692174 / R_kgDOABnSDg