chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

chipsalliance
chipsalliance
Date Created 2019-08-07 (5 years ago)
Commits 170 (last one 3 months ago)
Stargazers 291 (0 this week)
Watchers 27 (0 this week)
Forks 67
License unknown
Ranking

RepositoryStats indexes 584,353 repositories, of these chipsalliance/VeeRwolf is ranked #136,057 (77th percentile) for total stargazers, and #81,376 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #77/535.

chipsalliance/VeeRwolf is also tagged with popular topics, for these it's ranked: tools (#319/901)

Other Information

chipsalliance/VeeRwolf has Github issues enabled, there are 21 open issues and 38 closed issues.

There have been 8 releases, the latest one was published on 2021-09-13 (3 years ago) with the name SweRVolf 0.7.4.

All Topics
veer swerv tools fusesoc

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

21 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-13 @ 02:43pm, id: 201076719 / R_kgDOC_wv7w