enjoy-digital / usb3_pipe

USB3 PIPE interface for Xilinx 7-Series

Date Created 2019-09-16 (4 years ago)

Commits 291 (last one 2 years ago)

Stargazers 189 (0 this week)

Watchers 29 (0 this week)

Forks 31

License bsd-2-clause

Ranking

RepositoryStats indexes 535,551 repositories, of these enjoy-digital/usb3_pipe is ranked #175,412 (67th percentile) for total stargazers, and #74,257 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #104/461.

Other Information

enjoy-digital/usb3_pipe has Github issues enabled, there are 6 open issues and 22 closed issues.

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

19 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-07-02 @ 03:33am, id: 208852968 / R_kgDODHLX6A