gnodipac886 / ViT-FPGA-TPU

FPGA based Vision Transformer accelerator (Harvard CS205)

gnodipac886
gnodipac886
Date Created 2023-06-08 (about a year ago)
Commits 16 (last one about a month ago)
Stargazers 106 (0 this week)
Watchers 3 (0 this week)
Forks 12
License unknown
Ranking

RepositoryStats indexes 631,351 repositories, of these gnodipac886/ViT-FPGA-TPU is ranked #294,715 (53rd percentile) for total stargazers, and #417,031 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #74/195.

Other Information

gnodipac886/ViT-FPGA-TPU has Github issues enabled, there is 1 open issue and 2 closed issues.

Star History

Github stargazers over time

120120100100808060604040202000Jul '23Jul '23Aug '23Aug '23Sep '23Sep '23Oct '23Oct '23Nov '23Nov '23Dec '23Dec '2320242024Feb '24Feb '24Mar '24Mar '24Apr '24Apr '24May '24May '24Jun '24Jun '24Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Watcher History

Github watchers over time, collection started in '23

44443333332222Feb '24Feb '24Mar '24Mar '24Apr '24Apr '24May '24May '24Jun '24Jun '24Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Recent Commit History

16 commits on the default branch (main) since jan '22

16161414121210108866442200Jul '23Jul '23Aug '23Aug '23Sep '23Sep '23Oct '23Oct '23Nov '23Nov '23Dec '23Dec '2320242024Feb '24Feb '24Mar '24Mar '24Apr '24Apr '24May '24May '24Jun '24Jun '24Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Yearly Commits

Commits to the default branch (main) per year

2222111111000020242024

Issue History

Total Issues
Open Issues
Closed Issues
332.52.5221.51.5110.50.500Apr '24Apr '24May '24May '24Jun '24Jun '24Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogVerilogVerilogC++C++TclTclCCMakefileMakefileShellShellVHDLVHDLPythonPythonCMakeCMakeOtherOther

updated: 2025-03-22 @ 12:20pm, id: 651198133 / R_kgDOJtB-tQ