intel / fpga-partial-reconfig

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

intel
intel
Date Created 2016-12-01 (8 years ago)
Commits 234 (last one 7 months ago)
Stargazers 88 (0 this week)
Watchers 28 (0 this week)
Forks 42
License mit
Ranking

RepositoryStats indexes 600,333 repositories, of these intel/fpga-partial-reconfig is ranked #322,470 (46th percentile) for total stargazers, and #78,955 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #85/183.

Other Information

intel/fpga-partial-reconfig has Github issues enabled, there is 1 open issue and 2 closed issues.

There have been 5 releases, the latest one was published on 2018-05-28 (6 years ago) with the name Release notes for 18.0.0_1 release.

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Recent Commit History

24 commits on the default branch (master) since jan '22

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The primary language is SystemVerilog but there's also others...

updated: 2024-12-31 @ 11:11pm, id: 75342424 / R_kgDOBH2iWA