jjejdhhd / License-Plate-Recognition-FPGA

基于FPGA进行车牌识别

Date Created 2023-05-17 (about a year ago)
Commits 57 (last one about a year ago)
Stargazers 57 (1 this week)
Watchers 2 (0 this week)
Forks 13
License unknown
Ranking

RepositoryStats indexes 579,555 repositories, of these jjejdhhd/License-Plate-Recognition-FPGA is ranked #421,213 (27th percentile) for total stargazers, and #476,089 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #347/533.

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Recent Commit History

57 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-11-05 @ 04:04pm, id: 641714494 / R_kgDOJj_JPg