lieat05 / asic_pipe7_vpu

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lieat05
lieat05
Date Created 2025-01-01 (2 months ago)
Commits 2 (last one 2 months ago)
Stargazers 25 (0 this week)
Watchers 1 (0 this week)
Forks 0
License unknown
Ranking

RepositoryStats indexes 621,960 repositories, of these lieat05/asic_pipe7_vpu is ranked #614,238 (1st percentile) for total stargazers, and #560,575 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #599/607.

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

2 commits on the default branch (main) since jan '22

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Yearly Commits

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogC++C++CCMakefileMakefile

updated: 2025-01-16 @ 06:42pm, id: 910755617 / R_kgDONkkHIQ