MiSTeX-devel / MiSTeX-ports

FPGA board support and core ports for MiSTeX

Date Created 2023-03-04 (about a year ago)
Commits 419 (last one about a month ago)
Stargazers 44 (0 this week)
Watchers 9 (0 this week)
Forks 15
License bsd-3-clause
Ranking

RepositoryStats indexes 535,551 repositories, of these MiSTeX-devel/MiSTeX-ports is ranked #459,898 (14th percentile) for total stargazers, and #216,734 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #381/461.

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

419 commits on the default branch (main) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-06-27 @ 03:20am, id: 609452923 / R_kgDOJFODew