OpenXiangShan / XS-Verilog-Library

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OpenXiangShan
OpenXiangShan
Date Created 2021-07-01 (3 years ago)
Commits 38 (last one 3 years ago)
Stargazers 41 (0 this week)
Watchers 9 (0 this week)
Forks 12
License unknown
Ranking

RepositoryStats indexes 635,117 repositories, of these OpenXiangShan/XS-Verilog-Library is ranked #542,055 (15th percentile) for total stargazers, and #218,262 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #159/195.

Other Information

OpenXiangShan/XS-Verilog-Library has 1 open pull request on Github, 12 pull requests have been merged over the lifetime of the repository.

Star History

Github stargazers over time

45454040353530302525202015151010550020222022Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Watcher History

Github watchers over time, collection started in '23

1010101010109.59.5999999Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Recent Commit History

16 commits on the default branch (main) since jan '22

16161414121210108866442200Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (main) per year

25252020151510105500202120212022202220242024

Issue History

No issues have been posted

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogStataStata

updated: 2025-03-14 @ 05:17am, id: 381896328 / R_kgDOFsNGiA