RoaLogic / RV12

RISC-V CPU Core

Date Created 2017-01-11 (7 years ago)

Commits 595 (last one 5 months ago)

Stargazers 289 (1 this week)

Watchers 21 (0 this week)

Forks 50

License other

Ranking

RepositoryStats indexes 584,777 repositories, of these RoaLogic/RV12 is ranked #136,821 (77th percentile) for total stargazers, and #105,328 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #30/173.

RoaLogic/RV12 is also tagged with popular topics, for these it's ranked: cpu (#107/284), risc-v (#69/263)

Other Information

RoaLogic/RV12 has Github issues enabled, there are 4 open issues and 11 closed issues.

There have been 5 releases, the latest one was published on 2018-09-11 (6 years ago) with the name v1.3: RV12 32/64 Bit RISC-V CPU.

All Topics

cpu 64bit 32-bit risc-v

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

312 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-21 @ 03:37pm, id: 78653596 / R_kgDOBLAonA