russdill / bch_verilog

Verilog based BCH encoder/decoder

russdill
russdill
Date Created 2014-03-31 (10 years ago)
Commits 257 (last one 2 years ago)
Stargazers 112 (1 this week)
Watchers 8 (0 this week)
Forks 44
License other
Ranking

RepositoryStats indexes 579,555 repositories, of these russdill/bch_verilog is ranked #267,262 (54th percentile) for total stargazers, and #244,081 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #203/533.

Other Information

russdill/bch_verilog has Github issues enabled, there are 4 open issues and 4 closed issues.

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Recent Commit History

2 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-11-05 @ 08:12pm, id: 18290456 / R_kgDOARcXGA