suisuisi / basic_systemverilog

Must-have verilog systemverilog modules

suisuisi
suisuisi
Date Created 2022-05-01 (2 years ago)
Commits 2 (last one 2 years ago)
Stargazers 31 (0 this week)
Watchers 3 (0 this week)
Forks 10
License mit
Ranking

RepositoryStats indexes 621,960 repositories, of these suisuisi/basic_systemverilog is ranked #586,400 (6th percentile) for total stargazers, and #435,371 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #570/607.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

2 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogVHDLVHDLHTMLHTMLSystemVerilogSystemVerilogVVC++C++JavaJavaOtherOtherTclTclCCStataStata

updated: 2025-02-22 @ 12:59am, id: 487568919 / R_kgDOHQ-2Fw