ultraembedded / core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

ultraembedded
ultraembedded
Date Created 2020-07-14 (4 years ago)
Commits 8 (last one 3 years ago)
Stargazers 418 (6 this week)
Watchers 19 (0 this week)
Forks 94
License unknown
Ranking

RepositoryStats indexes 621,960 repositories, of these ultraembedded/core_ddr3_controller is ranked #107,355 (83rd percentile) for total stargazers, and #118,059 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #58/607.

Other Information

ultraembedded/core_ddr3_controller has Github issues enabled, there are 2 open issues and 3 closed issues.

Star History

Github stargazers over time

45045040040035035030030025025020020015015010010050500020212021Jul '21Jul '2120222022Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Watcher History

Github watchers over time, collection started in '23

191918181717161615151414131320232023Feb '23Feb '23Apr '23Apr '23Jun '23Jun '23Aug '23Aug '23Oct '23Oct '23Dec '23Dec '23Feb '24Feb '24Apr '24Apr '24Jun '24Jun '24Aug '24Aug '24Oct '24Oct '24Dec '24Dec '24Feb '25Feb '25

Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

776655443322110020202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
554.54.5443.53.5332.52.5221.51.5110.50.500Jul '21Jul '2120222022Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogMakefileMakefile

updated: 2025-03-01 @ 08:33am, id: 279706403 / R_kgDOEKv7Iw