WeiChungWu / vim-SystemVerilog

SystemVerilog syntax highlight/indent support in vim

WeiChungWu
WeiChungWu
Date Created 2012-06-06 (12 years ago)
Commits 22 (last one 4 years ago)
Stargazers 50 (0 this week)
Watchers 9 (0 this week)
Forks 18
License mit
Ranking

RepositoryStats indexes 630,031 repositories, of these WeiChungWu/vim-SystemVerilog is ranked #489,430 (22nd percentile) for total stargazers, and #217,390 for total watchers. Github reports the primary language for this repository as Vim Script, for repositories using this language it is ranked #1,391/1,500.

WeiChungWu/vim-SystemVerilog is also tagged with popular topics, for these it's ranked: vim (#1,364/1519),  syntax-highlighting (#306/346)

Other Information

WeiChungWu/vim-SystemVerilog has 1 open pull request on Github, 1 pull request has been merged over the lifetime of the repository.

Github issues are enabled, there are 2 open issues and 3 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
554.54.5443.53.5332.52.5221.51.5110.50.5002015201520162016201720172018201820192019202020202021202120222022202320232024202420252025

Languages

The only known language in this repository is Vim Script

Vim ScriptVim Script

updated: 2025-01-03 @ 03:57pm, id: 4569684 / R_kgDOAEW6VA