Xilinx / xup_embedded_system_design_flow

AMD Xilinx University Program Embedded tutorial

Xilinx
Xilinx
Date Created 2023-01-17 (about a year ago)
Commits 19 (last one about a year ago)
Stargazers 29 (0 this week)
Watchers 3 (0 this week)
Forks 8
License mit
Ranking

RepositoryStats indexes 535,551 repositories, of these Xilinx/xup_embedded_system_design_flow is ranked #520,802 (3rd percentile) for total stargazers, and #399,428 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #453/461.

Other Information

Xilinx/xup_embedded_system_design_flow has Github issues enabled, there is 1 open issue and 0 closed issues.

Homepage URL: https://xilinx.github.io/xup_embedded_system_design_flow/

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19 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-06-29 @ 06:55am, id: 590180293 / R_kgDOIy1vxQ