chipsalliance / UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Date Created 2019-12-13 (5 years ago)
Commits 2,184 (last one 2 days ago)
Stargazers 210 (0 this week)
Watchers 17 (0 this week)
Forks 41
License apache-2.0
Ranking

RepositoryStats indexes 624,936 repositories, of these chipsalliance/UHDM is ranked #180,310 (71st percentile) for total stargazers, and #126,481 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #10,163/33,358.

chipsalliance/UHDM is also tagged with popular topics, for these it's ranked: serialization (#167/396)

Other Information

chipsalliance/UHDM has Github issues enabled, there are 16 open issues and 101 closed issues.

There have been 2 releases, the latest one was published on 2024-08-07 (7 months ago) with the name 1.84 Latest stable.

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Recent Commit History

975 commits on the default branch (master) since jan '22

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Issue History

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Languages

The primary language is C++ but there's also others...

C++C++CCPythonPythonCMakeCMakeMakefileMakefileSWIGSWIGNixNixCap'n ProtoCap'n Proto

updated: 2025-03-09 @ 12:35am, id: 227755581 / R_kgDODZNGPQ