DOUDIU / Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm

The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

Date Created 2022-11-22 (2 years ago)
Commits 26 (last one 9 months ago)
Stargazers 32 (0 this week)
Watchers 1 (0 this week)
Forks 6
License unknown
Ranking

RepositoryStats indexes 632,894 repositories, of these DOUDIU/Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm is ranked #590,065 (7th percentile) for total stargazers, and #556,799 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #573/618.

DOUDIU/Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm is also tagged with popular topics, for these it's ranked: fpga (#503/515)

Other Information

DOUDIU/Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm has Github issues enabled, there is 1 open issue and 3 closed issues.

Star History

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Recent Commit History

26 commits on the default branch (main) since jan '22

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Issue History

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Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogC++C++MATLABMATLAB

updated: 2025-03-18 @ 04:48am, id: 569260662 / R_kgDOIe46dg