eminfedar / fedar-f1-rv64im

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

Date Created 2021-05-04 (3 years ago)
Commits 23 (last one 3 years ago)
Stargazers 198 (0 this week)
Watchers 8 (0 this week)
Forks 20
License mit
Ranking

RepositoryStats indexes 618,350 repositories, of these eminfedar/fedar-f1-rv64im is ranked #186,762 (70th percentile) for total stargazers, and #249,094 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #116/601.

eminfedar/fedar-f1-rv64im is also tagged with popular topics, for these it's ranked: riscv (#71/175),  core (#43/121)

Other Information

eminfedar/fedar-f1-rv64im has Github issues enabled, there is 1 open issue and 2 closed issues.

There have been 1 release, the latest one was published on 2021-05-23 (3 years ago) with the name v1.0.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

0 commits on the default branch (main) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
Open Issues
Closed Issues
332.52.5221.51.5110.50.50020222022Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogShellShellAssemblyAssembly

updated: 2025-02-09 @ 09:07am, id: 364403964 / R_kgDOFbhc_A