eminfedar / fedar-f1-rv64im

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

eminfedar
eminfedar
Date Created 2021-05-04 (3 years ago)
Commits 23 (last one 3 years ago)
Stargazers 196 (2 this week)
Watchers 8 (0 this week)
Forks 19
License mit
Ranking

RepositoryStats indexes 595,856 repositories, of these eminfedar/fedar-f1-rv64im is ranked #183,775 (69th percentile) for total stargazers, and #246,776 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #115/563.

eminfedar/fedar-f1-rv64im is also tagged with popular topics, for these it's ranked: riscv (#70/167),  core (#43/118)

Other Information

eminfedar/fedar-f1-rv64im has Github issues enabled, there is 1 open issue and 2 closed issues.

There have been 1 release, the latest one was published on 2021-05-23 (3 years ago) with the name v1.0.

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0 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-12-20 @ 09:29am, id: 364403964 / R_kgDOFbhc_A