FPGAwars / FPGA-peripherals

:seedling: :snowflake: Collection of open-source peripherals in Verilog

Date Created 2015-12-07 (9 years ago)
Commits 112 (last one 2 years ago)
Stargazers 173 (0 this week)
Watchers 18 (0 this week)
Forks 35
License gpl-2.0
Ranking

RepositoryStats indexes 622,366 repositories, of these FPGAwars/FPGA-peripherals is ranked #206,440 (67th percentile) for total stargazers, and #124,436 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #133/607.

FPGAwars/FPGA-peripherals is also tagged with popular topics, for these it's ranked: verilog (#108/302)

Other Information

FPGAwars/FPGA-peripherals has Github issues enabled, there are 4 open issues and 1 closed issue.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

18181818181817.517.517171717171720232023Feb '23Feb '23Apr '23Apr '23Jun '23Jun '23Aug '23Aug '23Oct '23Oct '23Dec '23Dec '23Feb '24Feb '24Apr '24Apr '24Jun '24Jun '24Aug '24Aug '24Oct '24Oct '24Dec '24Dec '24Feb '25Feb '25

Recent Commit History

9 commits on the default branch (master) since jan '22

99887766554433221100Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
554.54.5443.53.5332.52.5221.51.5110.50.500201720172018201820192019202020202021202120222022202320232024202420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogMakefileMakefilePythonPython

updated: 2025-01-05 @ 01:35pm, id: 47573604 / R_kgDOAtXqZA