manili / VSDBabySoC

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

manili
manili
Date Created 2021-08-05 (3 years ago)
Commits 114 (last one 3 years ago)
Stargazers 38 (0 this week)
Watchers 6 (0 this week)
Forks 12
License apache-2.0
Ranking

RepositoryStats indexes 632,869 repositories, of these manili/VSDBabySoC is ranked #557,830 (12th percentile) for total stargazers, and #289,747 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #540/622.

manili/VSDBabySoC is also tagged with popular topics, for these it's ranked: risc-v (#256/283)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

2 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogMakefileMakefilePerlPerlTclTcl

updated: 2025-03-12 @ 07:26pm, id: 392935370 / R_kgDOF2u3yg