SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Date Created 2017-07-27 (6 years ago)

Commits 196 (last one 3 years ago)

Stargazers 2,554 (2 this week)

Watchers 229 (0 this week)

Forks 995

License apache-2.0

This repository has been archived on Github

Ranking

RepositoryStats indexes 533,807 repositories, of these SI-RISCV/e200_opensource is ranked #18,865 (96th percentile) for total stargazers, and #5,770 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #2/456.

SI-RISCV/e200_opensource is also tagged with popular topics, for these it's ranked: verilog (#5/257), risc-v (#9/224), core (#6/107), china (#18/107)

Other Information

SI-RISCV/e200_opensource has 6 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 27 open issues and 16 closed issues.

Homepage URL: https://github.com/riscv-mcu/e203_hbirdv2

All Topics

cpu core china nuclei risc-v verilog ultra-low-power

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updated: 2024-06-26 @ 11:41am, id: 98553575 / R_kgDOBd_O5w