SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Date Created 2017-07-27 (7 years ago)
Commits 196 (last one 3 years ago)
Stargazers 2,663 (0 this week)
Watchers 230 (0 this week)
Forks 1,024
License apache-2.0
This repository has been archived on Github
Ranking

RepositoryStats indexes 618,350 repositories, of these SI-RISCV/e200_opensource is ranked #19,760 (97th percentile) for total stargazers, and #5,814 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #2/601.

SI-RISCV/e200_opensource is also tagged with popular topics, for these it's ranked: verilog (#7/299),  cpu (#24/295),  risc-v (#12/271),  core (#6/121),  china (#19/117)

Other Information

SI-RISCV/e200_opensource has 6 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 27 open issues and 16 closed issues.

Homepage URL: https://github.com/riscv-mcu/e203_hbirdv2

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

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Issue History

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Languages

The primary language is Verilog but there's also others...

VerilogVerilogCCAssemblyAssemblyC++C++ScalaScalaMakefileMakefilePythonPythonTclTclShellShellPerlPerlOtherOther

updated: 2025-02-20 @ 07:01pm, id: 98553575 / R_kgDOBd_O5w