SinghCoder / Icarus_Verilog

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

Date Created 2019-08-21 (5 years ago)

Commits 52 (last one 3 years ago)

Stargazers 51 (0 this week)

Watchers 4 (0 this week)

Forks 24

License unknown

Ranking

RepositoryStats indexes 589,134 repositories, of these SinghCoder/Icarus_Verilog is ranked #459,263 (22nd percentile) for total stargazers, and #374,926 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #398/549.

SinghCoder/Icarus_Verilog is also tagged with popular topics, for these it's ranked: verilog (#241/284)

Other Information

SinghCoder/Icarus_Verilog has 1 open pull request on Github, 1 pull request has been merged over the lifetime of the repository.

Homepage URL: https://singhcoder.github.io/Icarus_Verilog/

All Topics

verilog verilog-snippets computer-architecture

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0 commits on the default branch (master) since jan '22

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Languages

The only known language in this repository is Verilog

updated: 2024-11-10 @ 10:09pm, id: 203597311 / R_kgDODCKl_w