stillwater-sc / RISC-V-TensorCore

Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra

Date Created 2021-06-26 (3 years ago)
Commits 19 (last one 2 years ago)
Stargazers 48 (0 this week)
Watchers 5 (0 this week)
Forks 15
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RepositoryStats indexes 589,134 repositories, of these stillwater-sc/RISC-V-TensorCore is ranked #476,356 (19th percentile) for total stargazers, and #333,644 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #411/549.

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updated: 2024-12-03 @ 07:28am, id: 380509965 / R_kgDOFq4fDQ