stillwater-sc / RISC-V-TensorCore

Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra

Date Created 2021-06-26 (3 years ago)
Commits 19 (last one 3 years ago)
Stargazers 50 (0 this week)
Watchers 5 (0 this week)
Forks 15
License mit
Ranking

RepositoryStats indexes 618,350 repositories, of these stillwater-sc/RISC-V-TensorCore is ranked #482,836 (22nd percentile) for total stargazers, and #339,715 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #434/601.

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Github watchers over time, collection started in '23

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0 commits on the default branch (main) since jan '22

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Languages

The primary language is Verilog but there's also others...

VerilogVerilogC++C++SystemVerilogSystemVerilogMakefileMakefileCMakeCMake

updated: 2025-02-14 @ 08:22am, id: 380509965 / R_kgDOFq4fDQ