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stillwater-sc
RISC-V-TensorCore stillwater-sc
15
48
mit
5
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
risc-v64 vector-processor reproducible-computation
Created 2021-06-26
19 commits to main branch, last one 2 years ago