4 results found Sort:
- Filter by Primary Language:
- C++ (2)
- Jupyter Notebook (1)
- SystemVerilog (1)
- +
Fast multi-thread FEC simulator & library of efficient digital communication algorithms for SDR.
Created
2016-06-07
4,134 commits to develop branch, last one about a month ago
Simple OFDM modem for transceiving datagrams
Created
2021-06-09
58 commits to master branch, last one 10 months ago
FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
Created
2023-01-06
89 commits to main branch, last one 6 months ago
Work being done on the DVB-receiver for Phase 4 Ground.
Created
2017-03-25
44 commits to master branch, last one 2 years ago