Trending repositories for language Bluespec

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

MIT6.175 & MIT6.375 Study Notes

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

MIT6.175 & MIT6.375 Study Notes

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

MIT6.175 & MIT6.375 Study Notes

PCIe library for the Xilinx 7 series FPGAs in the Bluespec language

MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)

Connectal is a framework for software-driven hardware development.

A collection of common Bluespec interfaces/modules.

MIT6.175 & MIT6.375 Study Notes

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

PCIe library for the Xilinx 7 series FPGAs in the Bluespec language

MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Connectal is a framework for software-driven hardware development.

A collection of common Bluespec interfaces/modules.