abdelazeem201 / ASIC-Design-Roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

Date Created 2021-02-27 (3 years ago)

Commits 83 (last one 27 days ago)

Stargazers 171 (2 this week)

Watchers 7 (0 this week)

Forks 25

License mit

Ranking

RepositoryStats indexes 535,551 repositories, of these abdelazeem201/ASIC-Design-Roadmap is ranked #189,134 (65th percentile) for total stargazers, and #259,130 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #117/461.

abdelazeem201/ASIC-Design-Roadmap is also tagged with popular topics, for these it's ranked: awesome (#1,673/2664), awesome-list (#1,618/2645), fpga (#152/435), hardware (#168/401), verilog (#98/257)

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fpga awesome verilog hardware awesome-list

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Recent Commit History

63 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-07-03 @ 01:18pm, id: 342916296 / R_kgDOFHB8yA