avakar / usbcorev

A full-speed device-side USB peripheral core written in Verilog.

avakar
avakar
Date Created 2013-05-10 (11 years ago)
Commits 18 (last one 4 years ago)
Stargazers 215 (1 this week)
Watchers 18 (0 this week)
Forks 40
License other
Ranking

RepositoryStats indexes 579,555 repositories, of these avakar/usbcorev is ranked #168,708 (71st percentile) for total stargazers, and #122,404 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #106/533.

avakar/usbcorev is also tagged with popular topics, for these it's ranked: fpga (#140/475),  usb (#107/297),  verilog (#91/280)

Other Information

avakar/usbcorev has 1 open pull request on Github, 1 pull request has been merged over the lifetime of the repository.

Github issues are enabled, there is 1 open issue and 3 closed issues.

All Topics
usb fpga verilog

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Recent Commit History

0 commits on the default branch (master) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-11-05 @ 05:58pm, id: 9987004 / R_kgDOAJhjvA