DFiantHDL / DFHDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

Date Created 2019-06-16 (4 years ago)

Commits 1,461 (last one 8 days ago)

Stargazers 71 (0 this week)

Watchers 5 (0 this week)

Forks 8

License lgpl-3.0

Ranking

RepositoryStats indexes 523,840 repositories, of these DFiantHDL/DFHDL is ranked #337,256 (36th percentile) for total stargazers, and #314,188 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #1,368/1,917.

DFiantHDL/DFHDL is also tagged with popular topics, for these it's ranked: fpga (#297/425)

Other Information

DFiantHDL/DFHDL has Github issues enabled, there are 2 open issues and 13 closed issues.

Homepage URL: https://dfianthdl.github.io/

All Topics

hdl asic fpga dataflow dataflow-programming

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Recent Commit History

975 commits on the default branch (main) since jan '22

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Languages

The only known language in this repository is Scala

updated: 2024-05-26 @ 08:28am, id: 192230005 / R_kgDOC3UydQ