LeiWang1999 / ZYNQ-NVDLA

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

LeiWang1999
LeiWang1999
Date Created 2021-04-23 (3 years ago)
Commits 86 (last one 2 years ago)
Stargazers 331 (0 this week)
Watchers 8 (0 this week)
Forks 67
License unknown
Ranking

RepositoryStats indexes 637,312 repositories, of these LeiWang1999/ZYNQ-NVDLA is ranked #130,465 (80th percentile) for total stargazers, and #238,608 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #70/629.

LeiWang1999/ZYNQ-NVDLA is also tagged with popular topics, for these it's ranked: fpga (#108/523),  verilog (#72/312)

Other Information

LeiWang1999/ZYNQ-NVDLA has Github issues enabled, there are 5 open issues and 25 closed issues.

There have been 1 release, the latest one was published on 2023-12-27 (about a year ago) with the name ZYNQ-NVDLA First Release.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

2 commits on the default branch (master) since jan '22

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Yearly Commits

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Issue History

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Languages

The primary language is Verilog but there's also others...

VerilogVerilogCCC++C++TeXTeXMakefileMakefileSystemVerilogSystemVerilogShellShellBitBakeBitBakePythonPythonBatchfileBatchfileOtherOther

updated: 2025-03-29 @ 07:21am, id: 360813256 / R_kgDOFYGSyA