oddball / ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Date Created 2013-09-14 (11 years ago)

Commits 233 (last one 4 months ago)

Stargazers 57 (0 this week)

Watchers 11 (0 this week)

Forks 19

License gpl-2.0

Ranking

RepositoryStats indexes 579,555 repositories, of these oddball/ipxact2systemverilog is ranked #421,213 (27th percentile) for total stargazers, and #190,647 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #79,848/115,123.

oddball/ipxact2systemverilog is also tagged with popular topics, for these it's ranked: verilog (#220/280)

Other Information

oddball/ipxact2systemverilog has Github issues enabled, there are 2 open issues and 10 closed issues.

All Topics

vhdl ip-xact verilog systemverilog

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Github watchers over time, collection started in '23

Recent Commit History

94 commits on the default branch (master) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-10-11 @ 12:09pm, id: 12833368 / R_kgDOAMPSWA