oddball / ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Date Created 2013-09-14 (11 years ago)
Commits 233 (last one 5 months ago)
Stargazers 57 (0 this week)
Watchers 11 (0 this week)
Forks 19
License gpl-2.0
Ranking

RepositoryStats indexes 584,777 repositories, of these oddball/ipxact2systemverilog is ranked #424,324 (27th percentile) for total stargazers, and #191,147 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #80,598/116,437.

oddball/ipxact2systemverilog is also tagged with popular topics, for these it's ranked: verilog (#222/282)

Other Information

oddball/ipxact2systemverilog has Github issues enabled, there are 2 open issues and 10 closed issues.

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

94 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Python but there's also others...

updated: 2024-10-11 @ 12:09pm, id: 12833368 / R_kgDOAMPSWA