rafaelcalcada / rvx

RISC-V microcontroller IP core developed in Verilog

Date Created 2020-05-03 (4 years ago)

Commits 964 (last one 2 days ago)

Stargazers 172 (0 this week)

Watchers 11 (0 this week)

Forks 22

License mit

Ranking

RepositoryStats indexes 640,560 repositories, of these rafaelcalcada/rvx is ranked #211,247 (67th percentile) for total stargazers, and #186,895 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #145/632.

rafaelcalcada/rvx is also tagged with popular topics, for these it's ranked: cpu (#136/297), risc-v (#105/286), microcontroller (#106/215), riscv (#77/181), mcu (#52/174), core (#51/124)

Other Information

There have been 6 releases, the latest one was published on 2025-03-20 (26 days ago) with the name RVX v3.0.

Homepage URL: https://rafaelcalcada.github.io/rvx/

All Topics

cpu mcu rvx spi core gpio uart riscv rv32i zicsr risc-v processor system-on-chip microcontroller

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

777 commits on the default branch (main) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2025-04-15 @ 10:00am, id: 261005281 / R_kgDOD46f4Q