rj45 / rj32

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

rj45
rj45
Date Created 2021-05-29 (3 years ago)
Commits 204 (last one 2 years ago)
Stargazers 109 (0 this week)
Watchers 6 (0 this week)
Forks 17
License mit
Ranking

RepositoryStats indexes 609,425 repositories, of these rj45/rj32 is ranked #282,153 (54th percentile) for total stargazers, and #302,703 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #224/590.

rj45/rj32 is also tagged with popular topics, for these it's ranked: simulation (#522/1037),  fpga (#243/498),  simulator (#176/345),  verilog (#149/297),  cpu (#174/295)

Other Information

rj45/rj32 has Github issues enabled, there are 7 open issues and 8 closed issues.

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

7 commits on the default branch (main) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

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rj45/rj32

updated: 2025-01-24 @ 01:56am, id: 371843749 / R_kgDOFinipQ