rj45 / rj32

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

Date Created 2021-05-29 (3 years ago)

Commits 204 (last one 2 years ago)

Stargazers 105 (0 this week)

Watchers 5 (0 this week)

Forks 17

License mit

Ranking

RepositoryStats indexes 595,856 repositories, of these rj45/rj32 is ranked #284,998 (52nd percentile) for total stargazers, and #335,688 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #221/563.

rj45/rj32 is also tagged with popular topics, for these it's ranked: simulation (#529/1017), fpga (#245/488), simulator (#176/336), verilog (#149/289), cpu (#174/285)

Other Information

rj45/rj32 has Github issues enabled, there are 7 open issues and 8 closed issues.

All Topics

cpu dvi vga fpga verilog processor simulator simulation

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

7 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

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updated: 2024-12-16 @ 06:05am, id: 371843749 / R_kgDOFinipQ