Tan-YiFan / DigitalLogic-Autumn2020

复旦大学 数字逻辑与部件设计实验 2020秋

Tan-YiFan
Tan-YiFan
Date Created 2020-08-22 (4 years ago)
Commits 91 (last one 3 years ago)
Stargazers 47 (0 this week)
Watchers 2 (0 this week)
Forks 12
License unknown
Ranking

RepositoryStats indexes 638,253 repositories, of these Tan-YiFan/DigitalLogic-Autumn2020 is ranked #511,475 (20th percentile) for total stargazers, and #484,929 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #474/630.

Tan-YiFan/DigitalLogic-Autumn2020 is also tagged with popular topics, for these it's ranked: systemverilog (#82/101)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

5 commits on the default branch (master) since jan '22

554.54.5443.53.5332.52.5221.51.5110.50.500Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogTclTcl

updated: 2025-04-07 @ 07:25am, id: 289493756 / R_kgDOEUFS_A