ultraembedded / core_usb_cdc

Basic USB-CDC device core (Verilog)

Date Created 2019-07-20 (5 years ago)
Commits 10 (last one 3 years ago)
Stargazers 76 (0 this week)
Watchers 7 (0 this week)
Forks 15
License lgpl-2.1
Ranking

RepositoryStats indexes 610,997 repositories, of these ultraembedded/core_usb_cdc is ranked #360,949 (41st percentile) for total stargazers, and #272,896 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #299/593.

ultraembedded/core_usb_cdc is also tagged with popular topics, for these it's ranked: fpga (#325/499),  usb (#203/306),  verilog (#198/298)

Other Information

ultraembedded/core_usb_cdc has Github issues enabled, there are 2 open issues and 3 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

443.53.5332.52.5221.51.5110.50.5002019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
554.54.5443.53.5332.52.5221.51.5110.50.500202020202021202120222022202320232024202420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogPythonPythonTclTcl

updated: 2025-01-19 @ 08:12am, id: 197954777 / R_kgDOC8yM2Q