ultraembedded / core_usb_cdc

Basic USB-CDC device core (Verilog)

ultraembedded
ultraembedded
Date Created 2019-07-20 (5 years ago)
Commits 10 (last one 3 years ago)
Stargazers 74 (0 this week)
Watchers 7 (0 this week)
Forks 16
License lgpl-2.1
Ranking

RepositoryStats indexes 589,134 repositories, of these ultraembedded/core_usb_cdc is ranked #358,091 (39th percentile) for total stargazers, and #270,214 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #291/549.

ultraembedded/core_usb_cdc is also tagged with popular topics, for these it's ranked: fpga (#318/482),  usb (#202/299),  verilog (#195/284)

Other Information

ultraembedded/core_usb_cdc has Github issues enabled, there are 2 open issues and 3 closed issues.

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Recent Commit History

0 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-11-28 @ 05:11pm, id: 197954777 / R_kgDOC8yM2Q